Renesas SH7781 - Manual (Page 1101)

21. Serial Communication Interface with FIFO (SCIF)
Rev.1.00 Jan. 10, 2008 Page 1071 of 1658
REJ09B0261-0100
21.4 Operation
21.4.1 Overview
The SCIF can perform serial communication in asynchronous mode, in which synchronization is
achieved character by character and in clocked synchronous mode, in which synchronization is
achieved with clock pulses. For details on asynchronous mode, see section 21.4.2, Operation in
Asynchronous Mode.
64-stage FIFO buffers are provided for both transmission and reception, reducing the CPU
overhead, and enabling fast and continuous communication to be performed.
SCIF_RTS and SCIF_CTS signals are also provided as modem control signals (only in channel 0).
The serial transfer format is selected using SCSMR as shown in table 21.4. The SCIF clock source
is determined by the combination of the C/
A bit in SCSMR and the CKE1 and CKE0 bits in
SCSCR, as shown in table 21.5.
Asynchronous Mode:
• Data length: Choice of 7 or 8 bits
• LSB first for data transmission and reception
• Choice of parity addition and addition of 1 or 2 stop bits (the combination of these parameters
determines the transfer format and character length)
• Detection of framing errors, parity errors, receive-FIFO-data-full state, overrun errors, receive-
data-ready state, and breaks, during reception
• Indication of the number of data bytes stored in the transmit and receive FIFO registers
• Choice of peripheral clock (Pck) or SCIF_SCK pin input as SCIF clock source
When peripheral clock is selected: The SCIF operates on the baud rate generator clock and can
output a clock with frequency of 16 times the bit rate.
When SCIF_SCK pin input is selected: A clock with frequency of 16 times the bit rate must be
input (the on-chip baud rate generator is not used).