Renesas SH7781 - Manual (Page 368)

10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 338 of 1658
REJ09B0261-0100
Program execution state
Interrupt
generated?
ICR0.MAI = 1?
SR.BL = 0 or
sleep mode?
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
NMI?
No
Yes
No
No
Yes
Is NMI input low?
Level 15
interrupt?
No
No
No
Set interrupt source
code in INTEVT
Save SR in SSR;
save PC in SPC;
save R15 in SGR
Set SR.IMASK to
accepted interrupt level
Branch to
exception handling routine
Is SR.IMASK level
14 or less?
Level 14
interrupt?
Level 1
interrupt?
NMI?
Is SR.IMASK level
13 or less?
Is SR.IMASK level
0?
ICR0.NMIB = 1?
CPUOPM.INTMU = 1?
Figure 10.5 Flowchart of Interrupt Operation