Renesas SH7781 - Manual (Page 775)

15. Clock Pulse Generator (CPG)
Rev.1.00 Jan. 10, 2008 Page 745 of 1658
REJ09B0261-0100
15.4.3 Frequency Display Register 1 (FRQMR1)
FRQMR1 is a 32-bit readable register that reads the division ratio of divider 2 for the CPU clock
(lck), the SuperHyway clock (SHck), the peripheral clock (Pck), the DDR clock (DDRck),the bus
clock (Bck), the GDTA clock (GAck), the DU clock (DUck), and the RAM clock (Uck).
FRQMR1 can only be accessed in longwords.
This register is initialized by only a power-on reset via the
PRESET pin or a WDT overflow.
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30
1 x x x x 1 0 0 x 1 0 0 1 0 0 0
BFST0 BFST1 BFST2 BFST3 SFST0 SFST1 SFST2 SFST3 UFST0 UFST1 UFST2 UFST3 IFST0 IFST1 IFST3 IFST2
R R R R R R R R R R R R R R R R
BIt:
Initial value:
R/W:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14
x x 0 1 x x 1 x x 0 1 0 x 1 0 0
PFST0 PFST1 PFST2 PFST3 S3FST0 S3FST1 S3FST2 S3FST3 S2FST0 S2FST1 S2FST2 S2FST3 MFST0 MFST1 MFST3 MFST2
R R R R R R R R R R R R R R R R
BIt:
Initial value:
R/W:
Note: The initial value (x: a bit whose value is undefined) depends on the settings of mode pins
MODE0 to MODE4, MODE11, and MODE12 on a power-on reset via the
PRESET pin.
See Table 15.3 or 15.4.
Bit Bit Name
Initial
Value R/W Description
31
30
29
28
IFST3
IFST2
IFST1
IFST0
0
0
0
1
R
R
R
R
Frequency division ratio of the CPU clock (Ick)
0001:
Ч 1/2
0010:
Ч 1/4
0011:
Ч 1/6
27
26
25
24
UFST3
UFST2
UFST1
UFST0
0
0
1
x
R
R
R
R
Frequency division ratio of the RAM clock (Uck)
0010:
Ч 1/4
0011:
Ч 1/6
23
22
21
20
SFST3
SFST2
SFST1
SFST0
0
0
1
x
R
R
R
R
Frequency division ratio of the SuperHyway clock
(SHck)
0010:
Ч 1/4
0011:
Ч 1/6