Renesas SH7781 - Manual (Page 242)

8. Caches
Rev.1.00 Jan. 10, 2008 Page 212 of 1658
REJ09B0261-0100
This LSI has an IC way prediction scheme to reduce power consumption. In addition, memory-
mapped associative writing, which is detectable as an exception, can be enabled by using the non-
support detection exception register (EXPMASK). For details, see section 5, Exception Handling.
31 5 4 2
LW0
32 bits
LW1
32 bits
LW2
32 bits
LW3
32 bits
LW4
32 bits
LW5
32 bits
LW6
32 bits
LW7
32 bits
6 bits
MMU
[12:5]
255 19 bits 1 bit 1 bit
Tag U V
Address array
(way 0 to way 3)
Data array
(way 0 to way3)
LRU
Entry selection Longword (LW) selection
Virtual address
3
8
22
19
0
Write data Read data
Hit signal
(Way 0 to way 3)
12 10 0
Comparison
Figure 8.1 Configuration of Operand Cache (Cache size = 32 Kbytes)