Renesas SH7781 - Manual (Page 1320)

25. Audio Codec Interface (HAC)
Rev.1.00 Jan. 10, 2008 Page 1290 of 1658
REJ09B0261-0100
25.5.5 Initialization Sequence
Figure 25.3 shows an example of the initialization sequence.
No
No
Yes
HAC module
initialization
External codec
device
initialization
START
HAC cold reset
(HACCR = H'0000 0A00)
Start transfer (receiver/transmitter)
(HACCR = H'0000 0220)
Enable TX/RX
(Set HACACR to H'05E0 0000: 20-bit DMA, TX slots and 2 atomic control)* 1
Codec ready?
(Set HACCCR to H'0000 8000: 20-bit DMA,
TX slots and 2 atomic control)* 1
Set DMAC *2
Set read address to #h'26 (Power-down mode Ctrl/Stat)
(Set HACCSAR to H'000A 6000)* 1
Off-chip codec internal status
ADC, DAC, Analog, REF = ready?
(Set HACCSDR to H'0000 00F0)* 1
Set read volume and sampling rate
(1) HACACR = H'0000 0000
(2) Set HACCSAR and HACCSDR
(3) HACACR = H'01E0 0000
Notes: 1. Register values are reference data.
2. For details on DMAC settings, refer to section 14, Direct Memory Access Controller (DMAC)
Figure 25.3 Initialization Sequence