Renesas SH7781 - Manual (Page 1656)

32. Electrical Characteristics
Rev.1.00 Jan. 10, 2008 Page 1626 of 1658
REJ09B0261-0100
The following figure shows the output load circuit.
I
OL
I
OH
C
L
R
T
Reference level
LSI output pin
DUT output
Figure 32.76 Output Load Circuit
Notes: 1. CL is the total value, including the capacitance of the test jig. The capacitance of each
pin is set to 30 pF.
2. RT = 50Ω (DDR pin, AUD pin)
3. IOL = 24.5 mA (DDR pin, AUD pin)
4 mA (PC pin)
2 mA (other pins)
IOH = –24.5 mA (DDR pin, AUD pin)
–4 mA (PC pin)
–2 mA (other pins)