Renesas SH7781 - Manual (Page 745)

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 715 of 1658
REJ09B0261-0100
SuperHyway
bus cycle
Read Write Read Write Read Write
DREQ
CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC CPU
Figure 14.9 DMA Transfer Timing Example in Burst Mode
(DREQ Low Level Detection)
(3)
Bus Mode and Channel Priority
Figure 14.10 shows the bus modes and channel priority in priority fixed mode.
In priority fixed mode (CH0 > CH1), when channel 1 is transferring in burst mode, the transfer of
channel 0 starts immediately if there is a transfer request to channel 0 with a higher priority.
At this time, if channel 0 is also in burst mode, the channel 1 transfer continues after the channel 0
transfer has completely ended. (Figure 14.10 (h))
When channel 0 is in cycle steal mode, channel 0 with a higher priority performs the transfer of
one transfer unit and the channel 1 transfer is continuously performed without releasing the bus
mastership. The bus mastership then switches between the two in the order channel 0, channel 1,
channel 0, and channel 1. (Figure 14.10 (d))
In other words, the bus status looks as if the CPU cycle reached after the transfer in cycle steal
mode is replaced with transfer in burst mode (the status is called "burst mode priority execution").
When multiple channels are operating in burst modes, the channel with the highest priority is
executed first.
When DMA transfer is executed in the multiple channels, the bus mastership is not given to the
bus master until all competing burst transfers are completed.
In round-robin mode, the priority changes according to the specification shown in figure 14.3.
However, the channel in cycle steal mode and the channel in burst mode cannot be mixed.