Renesas SH7781 User Manual
Page 666
13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 636 of 1658
REJ09B0261-0100
(3)
Accessing PCI I/O Space
Burst transfers are not supported in I/O transfers. Access within the size of 4-byte.
The PCI I/O address space is allocated from H'FD20 0000 to H'FE3F FFFF (2 Mbytes).
Address translation from SuperHyway bus to PCI local bus is shown below.
The lower 15 bits ([17:3]) of a SuperHyway bus address are sent without translation.
The middle bits ([20:18]) of a SuperHyway bus address are controlled by PCIIOBMR.
• PCIIOMR0 [20:18] B'111: PCI address [20:18] = SuperHyway bus address [20:18]
• PCIIOMR0 [20:18] B'000: PCI address [20:18] = PCIIOBR [20:18]
The upper eleven bits ([31:21]) of a SuperHyway bus address are replaced with bits 31 to 21 in
PCIIOBR.
SHwy bus address
PCI address
PCIIOBMR
PCIIOBR
mask
31 21
20
18
17
0
31 21
20
18
17
0
31 21
20
18
17
0
31 21
20
18
17
0
Figure 13.6 Access from SuperHyway Bus to PCI I/O Space (PCI Bus)
(4)
Accessing Internal Registers of This LSI
All internal registers, that is, PCIECR, PCI configuration registers, and PCI local registers can be
accessed through the CPU. 4-byte, 2-byte, and 1-byte transmission are supported.
(5)
Endian
The PCIC in this LSI supports both the big endian and little endian formats. Since the PCI bus
supports little endian, the PCIC supports both byte swapping and non-byte swapping.
The endian format setting is specified by the TBS bit in PCICR.