Renesas SH7781 User Manual
Page 607
13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 577 of 1658
REJ09B0261-0100
(15)
PCI Memory Base Address Register 1 (PCIMBAR1)
This register is the memory base address register of the PCI configuration register space header
that is defined in PCI local bus specification. PCIMBAR1 specifies the memory space 1 (local
address space 1) in this LSI internal bus (SuperHyway bus).
See section 13.4.4 (1), Accessing Memory Space in This LSI.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
ASI
LAT
LAP
MBA2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit:
Initial value:
SH R/W:
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
PCI R/W:
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
30
MBA1
MBA2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
Initial value:
SH R/W:
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PCI R/W:
Bit Bit
Name
Initial
Value R/W
Description
31 to 20 MBA1
H'000
SH: R/W
PCI: R/W
Memory Space 1 Base Address (upper 12 bits)
These bits specify the upper 12 bits of memory base
address for the local address space 1 (the address
space in the internal bus).
The valid bits of MBA1 depend on the capacity of the
local address space specified with LSR in PCILSR1.
LSR
Address space
Valid bits of
in PCILSR1
MBA1
[28:20]
B'0 0000 0000
1 Mbyte
[31:20]
B'0 0000 0001
2 Mbytes
[31:21]
B'0 0000 0011
4 Mbytes
[31:22]
B'0 0000 0111
8 Mbytes
[31:23]
B'0 0000 1111
16 Mbytes
[31:24]
B'0 0001 1111
32 Mbytes
[31:25]
B'0 0011 1111
64 Mbytes
[31:26]
B'0 0111 1111
128 Mbytes
[31:27]
B'0 1111 1111
256 Mbytes
[31:28]
B'1 1111 1111
512 Mbytes
[31:29]
Other than above: Setting prohibited