Renesas SH7781 - Manual (Page 813)

17. Power-Down Mode
Rev.1.00 Jan. 10, 2008 Page 783 of 1658
REJ09B0261-0100
17.2 Input/Output Pins
Table 17.2 shows the pins related to power-down mode.
Table 17.2 Pin Configuration
Pin name Function I/O Description
STATUS1 Processing state 1 Output Indicate the operating states of this LSI
STATUS0 Processing state 2 STATUS1 STATUS0 Operating states
H H Reset
H L Sleep mode
L L Normal operation
The STATUS1 pin is multiplexed with the DRAK1
(DMAC) and PK6 (GPIO) pins. The STATUS0 pin
is multiplexed with the DRAK0 (DMAC) and PK7
(GPIO) pins.
Note: L means low level, and H means high level.
17.3 Register Descriptions
Table 17.3 shows the list of registers. Table 17.4 shows the register states in each processing
mode.
Table 17.3 Register Configuration
Table 17.3 Register Configuration
Register Name Abbreviation R/W P4 Address
Area 7
Address Access
Size Sync
clock
Sleep control register SLPCR R/W H'FFC8 0020 H'1FC8 0020 32 Pck
Standby control register 0 MSTPCR0 R/W H'FFC8 0030 H'1FC8 0030 32 Pck
Standby control register 1 MSTPCR1 R/W H'FFC8 0034 H'1FC8 0034 32 Pck
Standby display register MSTPMR R H'FFC8 0044 H'1FC8 0044 32 Pck
Note: For details of MSTPCR0 and MSTPCR1, see figure 15.1.