Renesas SH7781 - Manual (Page 1147)

22. Serial I/O with FIFO (SIOF)
Rev.1.00 Jan. 10, 2008 Page 1117 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Description
1 RFUDF 0 R/W Receive FIFO Underflow
0: Indicates that no receive FIFO underflow occurs
1: Indicates that a receive FIFO underflow occurs
A receive FIFO underflow means that reading of SIRDR
has occurred when the receive FIFO is empty.
When a receive FIFO underflow occurs, the value of
data read from SIRDR is not guaranteed.
• This bit is valid when the RXE bit in SICTR is 1.
• When 1 is written to this bit, the contents are
cleared. Writing 0 to this bit is invalid.
• To enable the issuance of this interrupt source, set
the RFUDFE bit in SIIER is set to 1.
0 RFOVF 0 R/W Receive FIFO Overflow
0: Indicates that no receive FIFO overflow occurs
1: Indicates a receive FIFO overflow occurs
A receive FIFO overflow means that writing has
occurred when the receive FIFO is full.
When a receive FIFO overflow occurs, the SIOF
indicates overflow, and receive data is lost.
• This bit is valid when the RXE bit in SICTR is 1.
• When 1 is written to this bit, the contents are
cleared. Writing 0 to this bit is invalid.
• To enable the issuance of this interrupt source, set
the RFOVFE bit in SIIER is set to 1.