Renesas SH7781 - Manual (Page 1167)

22. Serial I/O with FIFO (SIOF)
Rev.1.00 Jan. 10, 2008 Page 1137 of 1658
REJ09B0261-0100
22.4.6 FIFO
(1) Overview
The transmit and receive FIFO systems of the SIOF have the following features.
• 16-stage 32-bit FIFOs for transmission and reception
• The FIFO pointer can be updated in one read or write cycle regardless of access size of the
CPU and DMAC. (One-stage 32-bit FIFO access cannot be divided into multiple accesses.)
(2) Transfer Request
The transfer request of the FIFO can be issued to the CPU or DMAC as the following interrupt
sources.
• FIFO transmit request: TDREQ (transmit interrupt source)
• FIFO receive request: RDREQ (receive interrupt source)
The request conditions for FIFO transmit or receive can be specified individually. The request
conditions for the FIFO transmit and receive are specified by the TFWM2 to TFWM0 bits and the
bits RFWM2 to RFWM0 in SIFCTR, respectively. Tables 22.11 and 22.12 summarize the
conditions to issue transmit request and those to issue receive request, respectively.
Table 22.11 Conditions to Issue Transmit Request
TFWM2 to
TFWM0 Number of
Requested Stages*
1 Transmit Request Used Areas
000 1 Empty area is 16 stages
100 4 Empty area is 12 stages or more
101 8 Empty area is 8 stages or more
110 12 Empty area is 4 stages or more
Smallest
111* 2 16 Empty area is 1 stage or more Largest
Notes: 1. The number of requested stages is the number of stages in transmit/receive FIFO.
2. Setting prohibited in DMA use.