Renesas SH7781 - Manual (Page 1448)

28. General Purpose I/O Ports (GPIO)
Rev.1.00 Jan. 10, 2008 Page 1418 of 1658
REJ09B0261-0100
28.2.17 Port A Data Register (PADR)
PADR is an 8-bit readable/writable register that stores port A data.
0 1 2 3 4 5 6 7
0 0 0 0 0 0 0 0
PA0DT PA1DT PA2DT PA3DT PA4DT PA5DT PA6DT PA7DT
R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
7 PA7DT 0* R/W
6 PA6DT 0* R/W
5 PA5DT 0* R/W
4 PA4DT 0* R/W
3 PA3DT 0* R/W
2 PA2DT 0* R/W
These bits store output data of a pin which is used as a
general-purpose output port. When the pin functions as
a general-purpose output port, reading the port will read
out the value of the corresponding bit of this register.
When the pin functions as a general-purpose input port,
reading the port will read out the status of the
corresponding pin.
1 PA1DT 0* R/W
0 PA0DT 0* R/W
Note: * When the bus mode is set to DU via the bus mode pins (MODE11 and MODE12), the
pin is initially used as a general-purpose input, and the pin status is read from this
register.