Renesas SH7781 - Manual (Page 1406)

27. NAND Flash Memory Controller (FLCTL)
Rev.1.00 Jan. 10, 2008 Page 1376 of 1658
REJ09B0261-0100
27.6 Interrupt Processing
The FLCTL has four interrupt sources. Each of the interrupt sources has its corresponding
interrupt flag. The interrupt request is generated independently if the interrupt is enabled by the
interrupt enable bit. The status error and ready/busy timeout error use the common FLSTE
interrupt.
Table 27.6 FLCTL Interrupt Requests
Interrupt Source Interrupt Flag Enable Bit Description
STERB STERINTE Status error FLSTE interrupt
BTOERB RBERINTE Ready/busy timeout error
FLTEND interrupt TREND TEINTE Transfer end
FLTRQ0 interrupt TRREQF0 TRINTE0 FIFO0 transfer request
FLTRQ1 interrupt TRREQF1 TRINTE1 FIFO1 transfer request
27.7 DMA Transfer Settings
The FLCTL can request DMA transfers separately to the data sector, FLDTFIFO, and control
code sector, FLECFIFO. Table 27.7 shows whether DMA transfer is enabled or disabled in each
access mode.
Table 27.7 DMA Transfer Settings
Sector Access Mode Command Access Mode
FLDTFIFO Enabled Enabled
FLECFIFO Enabled Disabled
For details on DMAC settings, see section 14, Direct Memory Access Controller (DMAC).