Renesas SH7781 - Manual (Page 1356)

26. Serial Sound Interface (SSI) Module
Rev.1.00 Jan. 10, 2008 Page 1326 of 1658
REJ09B0261-0100
(1) Slave Receiver
This mode allows the module to receive a serial bit stream from another device and store it in
memory.
The shift register clock can be supplied from an external device or from an internal clock.
The word select pin is used as an input flow control. Assuming that SWSP = 0 if SSI_WS is high
then the module will receive the bit stream in blocks of 32 bits, one data bit per clock. If SSI_WS
goes low then the module will complete the current 32-bit block and then stop any further
reception, until SSI_WS goes high again.
(2)
Slave Transmitter
This mode cannot be used.
(3) Master Receiver
This mode allows the SSI module to receive a serial bit stream from another device and store it in
memory.
The shift register clock can be supplied from an external device or from an internal clock.
The word select pin is used as an output flow control. The module always asserts the word select
signal to indicate it can receive more data continuously. It is the responsibility of the transmitting
device to ensure it can transmit data to the SSI module in time to ensure no data is lost.
(4) Master Transmitter
This mode allows the module to transmit a serial bit stream from internal memory to another
device.
The shift register clock can be supplied from an external device or from an internal clock.
The word select pin is used as an output flow control. The module always asserts the word select
signal to indicate it will transmit more data continuously. Word select signal is not asserted until
the first word is ready to transmit however. It is the responsibility of the receiving device to ensure
it can receive the serial data in time to ensure no data is lost.
When the configuration for data transfer is completed, the SSI module can work with the
minimum interaction with CPU. The CPU specifies settings for the SSI module and DMAC then
handles overflow/ underflow interrupts if required.