Renesas SH7781 - Manual (Page 308)

10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 278 of 1658
REJ09B0261-0100
Bit Name
Initial
Value R/W
Description
25 NMIB 0 R/W NMI Block Mode
Selects whether an NMI interrupt is held until the BL bit
in SR is cleared to 0 or detected immediately when the
BL bit in SR of the CPU is set to 1.
0: An NMI interrupt is held when the BL bit in SR is set
to 1 (initial value)
1: An NMI interrupt is not held when the BL bit in SR is
set to 1
Note: If interrupts are accepted with the BL bit in SR
set to 1, information saved for any previous
exception (SSR, SPC, SGR, and INTEVT) is lost.
24 NMIE 0 R/W NMI Edge Select
Selects whether an interrupt request signal to the NMI
pin is detected at the rising edge or the falling edge.
0: An interrupt request is detected at the falling edge of
NMI input (initial value)
1: An interrupt request is detected at the rising edge of
NMI input
23 IRLM0 * 1 * 2 0 R/W IRL Pin Mode 0
Selects whether IRQ/
IRL3 to IRQ/IRL0 are used as
encoded interrupt requests (IRL3 to IRL0) or as four
independent interrupts (IRQ3 to IRQ0 interrupts).
0: IRQ/
IRL3 to IRQ/IRL0 are used as the encoded
interrupt requests (initial value)
1: IRQ/
IRL3 to IRQ/IRL0 are used as four independent
interrupt requests
22 IRLM1 * 1 * 2 0 R/W IRL Pin Mode 1
Selects whether IRQ/
IRL7 to IRQ/IRL4 are used as 4-
bit level-encoded interrupt requests (IRL7 to IRL4
interrupts) or as four independent interrupts (IRQ7 to
IRQ4 interrupts).
0: IRQ/
IRL7 to IRQ/IRL4 are used as the 4-bit level-
encoded interrupt requests (initial value)
1: IRQ/
IRL7 to IRQ/IRL4 are used as four independent
interrupt requests