Renesas SH7781 - Manual (Page 1084)

21. Serial Communication Interface with FIFO (SCIF)
Rev.1.00 Jan. 10, 2008 Page 1054 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W
Description
1
0
CKE1
CKE0
0
0
R/W
R/W
Clock Enable 1, 0
These bits select the SCIF clock source and whether to
enable or disable the clock output from the SCIF_SCK
pin. The CKE1 and CKE0 bits are used together to
specify whether the SCIF_SCK pin functions as a serial
clock output pin or a serial clock input pin. Note
however that the CKE0 bit setting is valid only when an
internal clock is selected as the SCIF clock source
(CKE1 = 0). When an external clock is selected (CKE1
= 1), the CKE0 bit setting is invalid. The CKE1 and
CKE0 bit must be set before determining the SCIF's
operating mode with SCSMR.
• Asynchronous mode
00: Internal clock/SCIF_SCK pin functions as port
according to the SCSPTR settings
01: Internal clock/SCIF_SCK pin functions as clock
output* 4
1x: External clock/SCIF_SCK pin functions as clock
input* 5
• Clocked synchronous mode
0x: Internal clock/SCIF_SCK pin functions as
synchronization clock output
1x: External clock/SCIF_SCK pin functions as
synchronization clock input
Legend:
x: Don't care
Notes: 1. An RXI interrupt request can be canceled by reading 1 from the RDF or DR flag in
SCFSR, then clearing the flag to 0, or by clearing the RIE bit to 0. ERI and BRI interrupt
requests can be canceled by reading 1 from ER and BRK in SCFSR, or ORER flag in
SCFSR, then clearing the flag to 0, or by clearing the RIE and REIE bits to 0.
2. SCSMR and SCFCR settings must be made, the transmission format determined, and
the transmit FIFO reset (the TFCL bit in SCFCR set to 1), before the TE bit is set to 1.
3. SCSMR and SCFCR settings must be made, the reception format determined, and the
receive FIFO reset (the RFCL bit in SCFCR set to 1), before the RE bit is set to 1.
4. The output clock frequency is 16 times the bit rate.
5. The input clock frequency is 16 times the bit rate.
(For the relation between the value set in SCBRR and the baud rate generator, see
section 21.3.8, Bit Rate Register n (SCBRR).)