Renesas SH7781 - Manual (Page 1160)

22. Serial I/O with FIFO (SIOF)
Rev.1.00 Jan. 10, 2008 Page 1130 of 1658
REJ09B0261-0100
SIOF_SCK
SIOF_RXD
SIOF_TXD
SIOF_SYNC
1-bit delay
Start bit data
1 frame
SIOF_SCK
SIOF_RXD
SIOF_TXD
SIOF_SYNC
Lch. Start bit of left channel data
(1/2 frame length)
1 frame
No delay
Rch. Start bit of right channel data
(1/2 frame length)
(b) L/R
(a) Synchronous pulse
Figure 22.3 Serial Data Synchronization Timing
(2) Transmit/Receive Timing
The SIOF_TXD transmit timing and SIOF_RXD receive timing relative to the SIOF_SCK can be
set as the sampling timing in the following two ways. The transmit/receive timing is set by the
REDG bit in SIMDR.
• Falling-edge sampling
• Rising-edge sampling
Figure 22.4 shows the transmit/receive timing.