Renesas SH7781 - Manual (Page 384)

11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 354 of 1658
REJ09B0261-0100
11.3 Overview of Areas
11.3.1 Space Divisions
The LSI has a 32-bit virtual address space as the architecture. The virtual address space is divided
into five areas according to the upper address value. Also, the memory space of the local bus has a
29-bit address space, and it is divided into eight areas.
A virtual address can be allocated to any external address by the address changing unit (MMU).
For details, see section 7, Memory Management Unit (MMU). This section describes the local bus
address area division.
Various types of memory or PC cards can be connected to the external address seven areas as
shown in table 11.2 and the chip select signals (
CS0 to CS6, CE2A, and CE2B) are output for each
area.
CS0 is asserted when area 0 is accessed, and CS6 is asserted when areas 6 is accessed. When
the PCMCIA interface is selected for area 5 or 6,
CE2A or CE2B is asserted along with CS5 or
CS6, according to the accessed bytes.
H'0000 0000
H'8000 0000
H'A000 0000
H'C000 0000
H'E000 0000
H'FFFF FFFF
H'E400 0000
H'0000 0000
H'0400 0000
H'0800 0000
H'0C00 0000
H'1000 0000
H'1400 0000
H'1800 0000
H'1FFF FFFF
H'1C00 0000
Area 0 ( CS0)
Area 1 ( CS1)
Area 2 ( CS2)
Area 3 ( CS3)
Area 4 ( CS4)
Area 5 ( CS5)
Area 6 ( CS6)
Area 7 (Reserved)
P0 and U0 areas
P1 area
P2 area
P3 area
P4 area
P0 and U0 areas
256
P1 area
P2 area
P3 area
Store-queue area
P4 area
Notes 1. When the MMU is turned off (AT in MMUCR = 0), the upper 3 bits of the 32-bit address
are ignored and other bits are mapped in the 29-bit external addresses.
2. When the MMU is turned on (AT in MMUCR = 1), the P0, U0, P3 and store-queue areas
can be mapped in any external address using the TLB. For details, see section 7,
Memory Management Unit (MMU).
Store-queue area
Figure 11.2 Correspondence between Virtual Address Space and Local Bus Memory Space