8 interrupt dma control register (flintdmacr) – Renesas SH7781 User Manual
Page 1384
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27. NAND Flash Memory Controller (FLCTL)
Rev.1.00 Jan. 10, 2008 Page 1354 of 1658
REJ09B0261-0100
27.3.8
Interrupt DMA Control Register (FLINTDMACR)
FLINTDMACR is a 32-bit readable/writable register that enables or disables DMA transfer
requests or interrupts. A transfer request from the FLCTL to the DMAC is issued after each access
mode has started.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
FIFOTRG[1:0]
AC1
CLR
AC0
CLR
DREQ1
EN
DREQ0
EN
STE
RB
BTO
ERB
TRR
EQF1
TRR
EQF0
STER
INTE
RBER
INTE
TE
INTE
TR
INTE1
TR
INTE0
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