Camr1 – Renesas SH7781 User Manual
Page 1497
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29. User Break Controller (UBC)
Rev.1.00 Jan. 10, 2008 Page 1467 of 1658
REJ09B0261-0100
• CAMR1
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CAM
CAM
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit :
Initial value :
R/W:
Bit :
Initial value :
R/W:
Bit Bit
Name
Initial
Value R/W
Description
31 to 0
CAM
Undefined R/W
Compare Address Mask
Specifies the bits to be masked among the address
bits which are specified using the CAR1 register. (Set
the bits to be masked to 1.)
0: Address bits CA[n] are included in the break
condition.
1: Address bits CA[n] are masked and not included in
the break condition.
[n] = any values from 31 to 0
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