Renesas SH7781 - Manual (Page 717)

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 687 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Descriptions
11 to 8 RS[3:0] 0000 R/W Resource Select 3 to 0
Specify the transfer request source. To change the
transfer request source, the DMA enable (DE) bit
should be cleared to 0.
0000: External request, or dual address mode
0100: Auto-request
1000: On-chip peripheral module request
Selected by DMA extended resource selector
(DMARS0 to DMARS5)
Other than above: Setting prohibited
Note: External request specification is valid in only
CHCR0 to CHCR3. The external request cannot
be specified in CHCR4 to CHCR11.
7
6
DL
DS
0
0
R/W
R/W
DREQ Level and DREQ Edge Select
Specify the detecting method of the DREQ input and
the detecting level.
These bits are valid in only CHCR0 to CHCR3. Even in
channels 0 to 3, if the transfer request source is
specified as an on-chip peripheral module or if an auto-
request is specified, these bits are invalid.
00: DREQ detected in low level (DREQ)
01: DREQ detected at falling edge
10: DREQ detected in high level
11: DREQ detected at rising edge
5 TB 0 R/W Transfer Bus Mode
Specifies the bus mode for DMA transfers.
0: Cycle steal mode
1: Burst mode
Select cycle steal mode when the on-chip peripheral
module requests are specified. This bit can be set to 0
or 1 only for channels 0 to 5.
For channels 6 to 11, this bit cannot be set to 1. The
write value should always be 0.
4, 3 TS[1:0] 00 R/W DMA Transfer Size Specification
See the description of TS2 (bit 20).