Renesas SH7781 - Manual (Page 1002)

20. Graphics Data Translation Accelerator (GDTA)
Rev.1.00 Jan. 10, 2008 Page 972 of 1658
REJ09B0261-0100
(6) Buffer RAM
Buffer RAM consists of two SRAM units each with an 8-Kbyte capacity. The RAM is used to
store color conversion table data for CL functions (buffer RAM 0) and to store IDCT data for MC
functions (buffer RAM 1). The entire 16-Kbyte capacity of this buffer RAM is allocated to a
memory map seen from the CPU. Valid access sizes are 4, 8, 16 and 32 bytes, and invalid access
sizes are 1 and 2 bytes.
(7) Buffer RAM Interface
The buffer RAM interface controls access to the buffer RAM 0/1. When there is access contention
between the CPU and the color conversion table transfer unit or the IDCT data transfer unit, bus
arbitration is performed. The buffer RAM interface exists as two independent blocks for the two
buffer RAM units. Because there is no access contention even during simultaneous reading of
buffer RAM 0 by the color conversion table data transfer unit and reading of buffer RAM 1 by the
IDCT table transfer unit, processing delays due to wait states and so on do not occur.
(8) CL Function Block
This block realizes CL functions. Specifically, data in YUV 4:2:0 format is converted into YUV
4:2:2 format or into ARGB8888 format.
(9) MC Function Block
This block realizes MC functions. Specifically, estimated images are generated using motion
vectors.
(10) CL/MC Bus Interface
The CL/MC bus interface controls access to the CL/MC function block by the CPU.
(11)
Arbiter
When there is contention of access from each GADMAC in the GDTA to the SuperHyway bus,
bus arbitration is performed.