Renesas SH7781 - Manual (Page 567)

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 537 of 1658
REJ09B0261-0100
command, the constraint tRCD between the ACT command and READ command, and the
constraint tRAS between the ACT command and the PRE command are involved. The DBSC2
waits to issue commands until each of the constraints is satisfied.
MCK0,
MCK1
MA[14:11]
MA[9:0]
MBA[2:0]
MCKE
MCS
MRAS
MCAS
MWE
MA[10]
PRE
bank A
ACT
bank A
Valid
Valid
Valid
Invalid
READ
bank A
tRCD
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
MDQS[3:0]
MDQ[31:0]
MDM[3:0] Invalid
Invalid Invalid
Invalid
Invalid
PRE
bank A
SDRAM
command
Valid
Valid Valid
Valid
Valid
High level
CL
= 3 cycles
= 3 cycles
tRAS
= 9 cycles
tRP
= 3 cycles
Read data
Figure 12.14 tRP, tRCD, CL, and tRAS