Renesas SH7781 - Manual (Page 661)

13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 631 of 1658
REJ09B0261-0100
13.4.2 PCIC Initialization
After a power-on reset, the ENBL bit in PCIECR and the CFINIT bit in PCICR are cleared. At
this time, if the PCIC operates as the PCI bus host (host mode), device arbitration is not performed
on the PCI bus, and the bus mastership is always granted to the PCIC. When the PCIC does not
operate as host (normal mode), access from an external PCI device connected to the PCI bus is not
accepted, and retries are returned to the PCI bus. In addition, all accesses to the PCIC from the
CPU are invalid except the access to PCIECR (a write access is invalid and a read access will read
0), and read or write accesses to each register and the PCI bus is not executed.
To initialize the PCIC, follow the procedures below.
1. Set the ENBL bit in PCIECR to 1.
2. Initialize the PCI configuration register and PCI local register in the PCIC (while the CFINIT
bit is cleared to 0).
3. Set the CFINT bit in PCICR to 1.
On completion of initialization of the registers, set the CFINIT bit to 1. Then, arbitration is
enabled in host mode, and the access from the PCI bus can be accepted in normal mode.
Whether the PCIC is in host mode or normal mode, external PCI devices cannot be accessed from
the PCIC while the CFINIT bit is being cleared. Set the CFINIT bit to 1 before accessing an
external PCIC device.
Be sure to initialize the following registers while the CFINIT bit is being cleared (before setting to
1): PCICMD, PCISTATUS, PCISVID, PCISID, PCILSR0, PCILSR1, PCILAR0 and PCILAR1.