Renesas SH7781 - Manual (Page 404)

11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 374 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Description
15
⎯ 0
R Reserved
This bit is always read as 0. The write value should
always be 0.
14 to 12 IWRRS 111 R/W Idle Cycles between Read-Read in Same Space
These bits specify the number of idle cycles to be
inserted after the memory connected to the space is
accessed. The target cycles are read-read cycles in
which consecutive accesses are performed to the same
space. For details, see section 11.5.8, Wait Cycles
between Access Cycles.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 3 idle cycles inserted
100: 4 idle cycles inserted
101: 5 idle cycles inserted
110: 6 idle cycles inserted
111: 7 idle cycles inserted
11, 10 BST 01 R/W Burst Number
These bits specify the number of bursts when the burst
ROM interface is used. The MPX interface is not
affected.
00: 4 consecutive accesses (Can be used with 8-, 16-,
or 32-bit bus width)
01: 8 consecutive accesses (Can be used with 8-, 16-,
or 32-bit bus width)
10: 16 consecutive accesses (Can be used with 8-, or
16-bit bus width)
11: 32 consecutive accesses (Can be used with 8-bit
bus width)