Table 32.25 classification of pins, Figure 32.72 pciclk/dclkin clock input timing – Renesas SH7781 User Manual
Page 1653
32. Electrical Characteristics
Rev.1.00 Jan. 10, 2008 Page 1623 of 1658
REJ09B0261-0100
Table 32.25 Classification of Pins
Pin Classification
Display Input Control
Signal*
1
Display Output
Control Signal*
2
Digital Data for
Display*
3
Pin Name
PCIFRAME/VSYNC
IRDY/HSYNC
LOCK/ODDF
PCIFRAME/VSYNC
IRDY/HSYNC
LOCK/ODDF
TRDY/DISP
STOP/CDE
D32/AD0/DR0
D33/AD1/DR1
D34/AD2/DR2
D35/AD3/DR3
D36/AD4/DR4
D37/AD5/DR5
D38/AD6/DG0
D39/AD7/DG1
D40/AD8/DG2
D41/AD9/DG3
D42/AD10/DG4
D43/AD11/DG5
D44/AD12/DB0
D45/AD13/DB1
D46/AD14/DB2
D47/AD15/DB3
D48/AD16/DB4
D49/AD17/DB5
Note: *1, *2, and *3 correspond to the numbers with asterisk in figures 32.73 and 32.74.
t
DICYC
t
DCKIH
VIH
VIL
VIL
VIH
VIH
1/2V
DDQ
1/2V
DDQ
t
DCKIL
PCICLK/DCLKIN
(Input)
Figure 32.72 PCICLK/DCLKIN Clock Input Timing