Renesas SH7781 - Manual (Page 852)

19. Display Unit (DU)
Rev.1.00 Jan. 10, 2008 Page 822 of 1658
REJ09B0261-0100
• Display mode register (DSMR)
⎯ VSPM bit (VSYNC pin mode)
⎯ ODPM bit (ODPM pin mode)
⎯ ODDF bit (ODDF pin mode)
⎯ DIPM bit (DISP pin mode)
⎯ CSPM bit (HSYNC pin mode)
⎯ DIL bit (polarity reversal bit of the DISP pin)
⎯ VSL bit (polarity reversal bit of the VSYNC pin)
⎯ HSL bit (polarity reversal bit of the HSYNC pin)
• Output signal timing adjustment register (OTAR)
⎯ All bits
The registers for the X and Y start positions for plane n in the interlaced sync & video mode
(PnSPXR, PnSPYR) are also internally updated at the beginning of a field.
Internal updates at the beginning of each frame are performed at the falling edge of VSYNC
output when the sync method of DSYSR is master mode (TVM = 00), or at the falling edge of
EXVSYNC detected in TV sync mode (TVM = 10). In sync switching mode (TVM = 11), internal
updates are not performed, and data is retained.
The address-mapped registers with an internal update function are shown in table 19.2. The initial
settings for these registers should be made during the interval in which the DRES bit in DSYSR is
1. For other important information on the timing of register updates, please refer to the
explanations of each register.