Renesas SH7781 - Manual (Page 663)

13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 633 of 1658
REJ09B0261-0100
(2) Accessing PCI Memory Space
Figure 13.2 shows the memory map from the SuperHyway bus to the PCI bus.
PCI memory space 1
64 MB
PCI memory space 2
512 MB
SHwy bus address space (4 GB)
PCI memory space 0
16 MB
Register space 2 MB
PCI I/O space 2 MB
PCI address space (4 GB)
512 MB
64 MB
16 MB
H'0000 0000
H'1000 0000
H'C000 0000
H'FD00 0000
H'FE00 0000
H'FE20 0000
Figure 13.2 Memory Map from SuperHyway Bus to PCI Bus
To access the PCI memory space, use PCIMBR and PCIMBMR. These registers can allocate
address space ranging from 16 Mbytes to 512 Mbytes. PCI addresses can be allocated to by
software.
Burst transfers are supported for memory transfers.
Consecutive 32-byte burst accesses from the CPU or DMAC result in a burst transfer of 32 bytes
or more (64 bytes, 96 bytes, etc.) on the PCI bus.
The PCI memory spaces are allocated from H'FD00 0000 to H'FDFF FFFF for PCI memory space
0 (16 Mbytes), H'1000 0000 to H'13FF FFFF for PCI memory space 1 (64 Mbytes, selection of the
PCIC and LBSC spaces), and H'C000 0000 to H'DFFF FFFF for PCI memory space 2 (512
Mbytes, available only in 32-bit address extended mode).
Address translation from the SuperHyway bus to PCI local bus is shown below.
The lower 15 bits ([17:3]) of a SuperHyway bus address are sent without translation.