5 usage notes, 3 on-chip memory coherency – Renesas SH7781 User Manual
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9. On-Chip Memory
Rev.1.00 Jan. 10, 2008 Page 261 of 1658
REJ09B0261-0100
9.5
Usage Notes
9.5.1
Page Conflict
In the event of simultaneous access to the same page from different buses, page conflict occurs.
Although each access is completed correctly, this kind of conflict tends to lower OL memory
accessibility. Therefore it is advisable to provide all possible preventative software measures. For
example, conflicts will not occur if each bus accesses different pages.
9.5.2
Access Across Different Pages
(1)
OL Memory
Read access from the operand bus is performed in one cycle when the access is made successively
to the same page but takes multiple cycles (a maximum of two wait cycles may be required) when
the access is made across pages or the previous access was made to memory other than OL
memory. For this reason, from the viewpoint of performance optimization, it is recommended to
design the software such that the page corresponding to the address for read access from the
operand bus does not change so often.
(2)
IL Memory
Access from the instruction bus is performed in one cycle when the access is made successively to
the same page but takes multiple cycles (a maximum of two wait cycles may be required) when
the access is made across pages or the previous access was made to memory other than IL
memory. For this reason, from the viewpoint of performance optimization, it is recommended to
design the software such that the target page does not change so often in access from the
instruction bus. For example, allocating a separate program for each page will deliver better
efficiency.
9.5.3
On-Chip Memory Coherency
(1)
OL Memory
In order to allocate instructions in the OL memory, write an instruction to the OL memory,
execute the following sequence, then branch to the rewritten instruction.
• SYNCO
• ICBI @Rn
In this case, the target for the ICBI instruction can be any address (OL memory address may be
possible) within the range where no address error exception occurs, and cache hit/miss is possible.