Renesas SH7781 User Manual
Page 664
13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 634 of 1658
REJ09B0261-0100
For PCI memory space 0, the middle six bits ([23:18]) are controlled by PCIMBMR0.
• PCIMBMR0 [23:18] B'1111 11: PCI address [23:18] = SuperHyway bus address [23:18]
• PCIMBMR0 [23:18] B'0000 00: PCI address [23:18] = PCIMBR0 [23:18]
The upper eight bits ([31:24]) of a SuperHyway bus address are replaced with bits 31 to 24 in
PCIMBR0.
SHwy bus address
PCI address
PCIMBMR0
PCIMBR0
mask
31 24
23
18
17
0
31 24
23
18
17
0
31 24
23
18
17
0
31 24
23
18
17
0
Figure 13.3 Access from SuperHyway Bus to PCI Memory (PCI Bus)
(PCI Memory Space 0)
For PCI memory space 1 accesses, the middle eight bits ([25:18]) are controlled by PCIMBMR1.
• PCIMBMR1 [25:18] B'11 1111 11: PCI address [25:18] = SuperHyway bus address [25:18]
• PCIMBMR1 [25:18] B'00 0000 00: PCI address [25:18] = PCIMBR1 [25:18]
The upper six bits ([31:26]) of a SuperHyway bus address are replaced with bits 31 to 26 in
PCIMBR1.
SHwy bus address
PCI address
PCIMBMR1
PCIMBR1
mask
31 26 25
18
17
0
31 26 25
18
17
0
31 26
25
18
17
0
31 26
25
18
17
0
Figure 13.4 Access from SuperHyway Bus to PCI Memory (PCI Bus)
(PCI Memory Space 1)