Renesas SH7781 - Manual (Page 288)

9. On-Chip Memory
Rev.1.00 Jan. 10, 2008 Page 258 of 1658
REJ09B0261-0100
(1) When MMU is Enabled (MMUCR.AT = 1) and RAMCR.RP = 1
An address of the OL memory area is specified to the UTLB VPN field, and to the physical
address of the transfer source (in the case of the PREF instruction) or the transfer destination (in
the case of the OCBWB instruction) to the PPN field. The ASID, V, SZ, SH, PR, and D bits have
the same meaning as normal address conversion; however, the C and WT bits have no meaning in
this page.
When the PREF instruction is issued to the OL memory area, address conversion is performed in
order to generate the physical address bits [28:10] in accordance with the SZ bit specification. The
physical address bits [9:5] are generated from the virtual address prior to address conversion. The
physical address bits [4:0] are fixed to 0. Block transfer is performed to the OL memory from the
external memory which is specified by these physical addresses.
When the OCBWB instruction is issued to the OL memory area, address conversion is performed
in order to generate the physical address bits [28:10] in accordance with the SZ bit specification.
The physical address bits [9:5] are generated from the virtual address prior to address conversion.
The physical address bits [4:0] are fixed to 0. Block transfer is performed from the OL memory to
the external memory specified by these physical addresses.
In PREF or OCBWB instruction execution, an MMU exception is checked as read type. After the
MMU execution check, a TLB miss exception or protection error exception occurs if necessary. If
an exception occurs, the block transfer is inhibited.
(2) When MMU is Disabled (MMUCR.AT = 0) or RAMCR.RP = 0
The transfer source physical address in block transfer to page 0A or 0B in the OL memory is set in
the L0SADR bits of the LSA0 register. And the L0SSZ bits in the LSA0 register choose either the
virtual addresses specified through the PRFF instruction or the L0SADR values as bits 15 to 10 of
the transfer source physical address. In other words, the transfer source area can be specified in
units of 1 Kbyte to 64 Kbytes.
The transfer destination physical address in block transfer from page 0A or 0B in the OL memory
is set in the L0DADR bits of the LDA0 register. And the L0DSZ bits in the LDA0 register choose
either the virtual addresses specified through the OCBWB instruction or the L0DADR values as
bits 15 to 10 of the transfer destination physical address. In other words, the transfer source area
can be specified in units of 1 Kbyte to 64 Kbytes.
Block transfer to page 1A or 1B in the OL memory is set to LSA1 and LDA1 as with page 0A or
0B in the OL memory.