Renesas SH7781 - Manual (Page 251)

8. Caches
Rev.1.00 Jan. 10, 2008 Page 221 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W
Description
8 RP 0 R/W On-Chip Memory Protection Enable Bit
For details, see section 9.4, On-Chip Memory
Protective Functions.
7 IC2W 0 R/W IC Two-Way Mode bit
0: IC is a four-way operation
1: IC is a two-way operation
For details, see section 8.4.3, IC Two-Way Mode.
6 OC2W 0 R/W OC Two-Way Mode bit
0: OC is a four-way operation
1: OC is a two-way operation
For details, see section 8.3.6, OC Two-Way Mode.
5 ICWPD 0 R/W IC Way Prediction Stop
Selects whether the IC way prediction is used.
0: Instruction cache performs way prediction.
1: Instruction cache does not perform way prediction.
4 to 0
⎯ All
0 R Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.