Renesas SH7781 - Manual (Page 1001)

20. Graphics Data Translation Accelerator (GDTA)
Rev.1.00 Jan. 10, 2008 Page 971 of 1658
REJ09B0261-0100
(1) Target Interface
The target interface controls access by the CPU to the GDTA internal registers, buffer RAM 0/1,
and CL and MC function blocks (image processing function blocks). The target interface places a
request queue/response queue in the high-speed SuperHyway bus reception unit, and alleviates the
access load of the initiator on this bus.
(2) Initiator Interface
Four GADMAC channels are provided within the GDTA, for data control during DMA data
transfer between external memory and internal image processing function blocks.
(3)
GADMAC (CLR_GADMAC, CLW_GADMAC, MCR_GADMAC, MCW_GADMAC)
The GADMAC executes DMA control of data transfer between external memory and internal
image processing function blocks. A total of four channels are provided, including two channels
for CL functions and two channels for MC functions. The GADMAC is controlled through
registers within the CL function block and MC function block.
Applications of each of the channels are as follows.
CLR_GADMAC: Data transfer from external memory to the CL function block (read data
transfer)
CLW_GADMAC: Data transfer from the CL function block to external memory (write data
transfer)
MCR_GADMAC: Data transfer from external memory to the MC function block (read data
transfer)
MCW_GADMAC: Data transfer from the MC function block to external memory (write data
transfer)
* External memory: The external DDR2-SDRAM or the external memory connected to the
local bus.
(4) Color Conversion Table Control
In color conversion table control, color conversion table data is transferred between buffer RAM 0
and the CL function block.
(5)
IDCT Control
In IDCT control, IDCT data is transferred between the buffer RAM 1 and MC function block.