Renesas SH7781 User Manual
Page 284
9. On-Chip Memory
Rev.1.00 Jan. 10, 2008 Page 254 of 1658
REJ09B0261-0100
9.2.5
OL memory Transfer Destination Address Register 1 (LDA1)
When MMUCR.AT = 0 or RAMCR.RP = 0, LDA1 specifies the transfer destination physical
address for block transfer to page 1A or 1B in the OL memory.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Bit :
0
0
0
Initial value :
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
L1DADR
L1DADR
L1DSZ
R/W
R/W
R/W
R/W
R/W
R/W
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit :
0
0
0
0
Initial value :
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W:
Bit Bit
Name
Initial
Value R/W
Description
31 to 29 —
All 0
R
Reserved
For read/write in these bits, refer to General
Precautions on Handling of Product.
28 to 10 L1DADR
Undefined R/W
OL memory Page 1 Block Transfer Destination Address
When MMUCR.AT = 0 or RAMCR.RP = 0, these bits
specify transfer destination physical address for block
transfer to page 1A or 1B in the OL memory.
9 to 6
—
All 0
R
Reserved
For read/write in these bits, refer to General
Precautions on Handling of Product.