15 cl frame width setting register (clwr) – Renesas SH7781 User Manual
Page 1024
20. Graphics Data Translation Accelerator (GDTA)
Rev.1.00 Jan. 10, 2008 Page 994 of 1658
REJ09B0261-0100
20.3.15
CL Frame Width Setting Register (CLWR)
CLWR is in the CL register block and sets the input image width in pixel units.
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31
30
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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BIt:
Initial value:
R/W:
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CL_W
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R/W
R/W
R/W
R/W
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R/W
R/W
R/W
R/W
R/W
R/W
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BIt:
Initial value:
R/W:
Bit Bit
Name
Initial
Value R/W Description
31 to 12
⎯ All
0
⎯ Reserved
These bits are always read as 0. The write value should
always be 0.
11 to 0 CL_W
All 0
R/W
Frame width setting
Should be set in pixel units.
Value set should be 2 × n (n: an integer greater than 0)
Notes: 1. CL processing is prohibited when the setting is 0.
2. Addition is performed taking that 1 pixel = 1 byte.
3. CLWR (bytes) + CLIYPR (bytes) should be 32 bytes
× n (n: an integer greater than 0)
4. CLWR (bytes)/2 + CLUVPR (bytes) should be 32 bytes
× n (n: an integer greater than
0)