Renesas SH7781 - Manual (Page 853)

19. Display Unit (DU)
Rev.1.00 Jan. 10, 2008 Page 823 of 1658
REJ09B0261-0100
Table 19.2 Register Configuration
Register Name Abbr. R/W
P4
Address Area 7
Address Size Synchronous
Clock
Display control registers
Display system control register DSYSR R/W H'FFF80000 H'1FF80000 32 Pck
Display mode register DSMR R/W H'FFF80004 H'1FF80004 32 Pck
Display status register DSSR R H'FFF80008 H'1FF80008 32 Pck
Display status register clear
register DSRCR W H'FFF8000C H'1FF8000C 32 Pck
Display interrupt enable register DIER R/W H'FFF80010 H'1FF80010 32 Pck
Color palette control register CPCR R/W H'FFF80014 H'1FF80014 32 Pck
Display plane priority order
register DPPR R/W H'FFF80018 H'1FF80018 32 Pck
Display extension function
enable register DEFR R/W H'FFF80020 H'1FF80020 32 Pck
Display timing generation registers
Horizontal display start position
register HDSR R/W H'FFF80040 H'1FF80040 32 Pck
Horizontal display end position
register HDER R/W H'FFF80044 H'1FF80044 32 Pck
Vertical display start position
register VDSR R/W H'FFF80048 H'1FF80048 32 Pck
Vertical display end position
register VDER R/W H'FFF8004C H'1FF8004C 32 Pck
Horizontal scan period register HCR R/W H'FFF80050 H'1FF80050 32 Pck
Horizontal synchronous pulse
width register HSWR R/W H'FFF80054 H'1FF80054 32 Pck
Vertical scan period register VCR R/W H'FFF80058 H'1FF80058 32 Pck
Vertical synchronous position
register VSPR R/W H'FFF8005C H'1FF8005C 32 Pck
Equivalent pulse width register EQWR R/W H'FFF80060 H'1FF80060 32 Pck
Separation width register SPWR R/W H'FFF80064 H'1FF80064 32 Pck
CLAMP signal start position
register CLAMPSR R/W H'FFF80070 H'1FF80070 32 Pck
CLAMP signal width register CLAMPWR R/W H'FFF80074 H'1FF80074 32 Pck