Renesas SH7781 - Manual (Page 1659)

Appendix
Rev.1.00 Jan. 10, 2008 Page 1629 of 1658
REJ09B0261-0100
Table B.2 Area 0 Memory Type and Bus Width
Pin Value
MODE7 MODE6* MODE5 Memory Interface Bus Width
L L L MPX interface 64 bits
H Setting prohibited Setting prohibited
H L Setting prohibited Setting prohibited
H MPX interface 32 bits
H L L SRAM interface 64 bits
H SRAM interface 8 bits
H L SRAM interface 16 bits
H SRAM interface 32 bits
Note: * The MODE6 pin is output state after power-on reset.
Table B.3 Endian
Pin Value
MODE8 Endian
L Big endian
H Little endian
Table B.4 Master/Slave
Pin Value
MODE9 Master/Slave
L Slave
H Master
Table B.5 Clock Input
Pin Value
MODE10 Clock Input
L External input clock
H Crystal resonator