Renesas SH7781 User Manual
Page 440
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11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 410 of 1658
REJ09B0261-0100
(3)
Read-Strobe/Write-Strobe Timing
When the SRAM interface is used, the strobe signal negation timing in reading can be specified
with the RDSPL bit in CSnBCR. For details of settings, see section 11.4.3, CSn Bus Control
Register (CSnBCR). The RDSPL bit should be cleared to 0 when a byte control SRAM is
specified.
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