Figure 15.1 block diagram of the cpg – Renesas SH7781 User Manual
Page 764
15. Clock Pulse Generator (CPG)
Rev.1.00 Jan. 10, 2008 Page 734 of 1658
REJ09B0261-0100
Oscillator circuit
Control section
Crystal oscillator
circuit
Divider 1
× 1
PLL circuit 1
Ч 72
Ч 36
Clock frequency
control circuit
FRQCR0
FRQCR1
MSTPCR1
Clock control circuit
Bus interface
Peripheral bus
PLL circuit 2
× 1
CLKOUT
CLKOUTENB
Divider 2
Ч 1/2
Ч 1/4
Ч 1/6
Ч 1/8
Ч 1/12
Ч 1/16
Ч 1/18
Ч 1/24
Ч 1/32
Ч 1/36
Ч 1/48
Bus clock
(Bck)
CPU clock
(Ick)
SHwy clock
(SHck)
GA clock
(GAck)
DU clock
(DUck)
Peripheral clock
(Pck)
DDR clock
(DDRck)
RAM clock
(Uck)
XTAL
EXTAL
MODE 10
MODE 4
MODE 3
MODE 2
MODE 1
MODE 0
Legend:
FRQCR0: Frequency control register 0
FRQCR1: Frequency control register 1
MSTPCR1: Module standby control register 1*
Note: * For details about MSTPCR1, see section 17, Power-Down Mode.
Figure 15.1 Block Diagram of the CPG