Renesas SH7781 - Manual (Page 519)

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 489 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W
Description
23 to 20
⎯
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
19 to 16 TRAS3 to
TRAS0
0011 R/W tRAS (ACT-PRE period) Setting Bits
These bits set the ACT-PRE minimum period constraint
for the same bank. These bits should be set according
to the DDR2-SDRAM specifications. The number of
cycles is the number of DDR clock cycles.
0000: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
:
0010: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
0011: 4 cycles
0100: 5 cycles
:
1110: 15 cycles
1111: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
15
⎯
0 R Reserved
This bit is always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.