Renesas SH7781 - Manual (Page 523)

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 493 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W
Description
15 to 11
⎯
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
10 to 8 TRRD2 to
TRRD0 000 R/W tRRD (ACT(A)-ACT(B) period) Setting Bits
These bits set the ACT-ACT minimum period constraint
for the different banks. These bits should be set
according to the DDR2-SDRAM specifications. The
number of cycles is the number of DDR clock cycles.
000: 1 cycle
001: 2 cycles
010: 3 cycles
011: 4 cycles
100: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
:
111: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
7 to 3
⎯
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.