Renesas SH7781 - Manual (Page 266)

8. Caches
Rev.1.00 Jan. 10, 2008 Page 236 of 1658
REJ09B0261-0100
Address field
31 23 5 4 3 2 1 0
1 1 1 1 0 1 0 0 Entry A
Data field
31 10 9 1 0
V Tag
24 1312 14 15
2
U
V
U
A
: Validity bit
: Dirty bit
: Association bit
: Reserved bits (write value should be 0 and read value is undefined )
: Don't care
Way
0 0 0 0
* * * * * * * * *
*
Figure 8.7 Memory-Mapped OC Address Array (Cache size = 32 Kbytes)
8.6.4 OC Data Array
The OC data array is allocated to addresses H'F500 0000 to H'F5FF FFFF in the P4 area. A data
array access requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification. The way and entry to be accessed are specified in the address field, and
the longword data to be written is specified in the data field.
In the address field, bits [31:24] have the value H'F5 indicating the OC data array, and the way is
specified by bits [14:13] and the entry by bits [12:5]. Address field bits [4:2] are used for the
longword data specification in the entry. As only longword access is used, 0 should be specified
for address field bits [1:0].
The data field is used for the longword data specification.
The following two kinds of operation can be used on the OC data array:
1. OC data array read
Longword data is read into the data field from the data specified by the longword specification
bits in the address field in the OC entry corresponding to the way and entry set in the address
field.
2. OC data array write
The longword data specified in the data field is written for the data specified by the longword
specification bits in the address field in the OC entry corresponding to the way and entry set in
the address field. This write does not set the U bit to 1 on the address array side.