Renesas SH7781 - Manual (Page 575)

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 545 of 1658
REJ09B0261-0100
write
MCK
Command
Data
MCKE
MODT
Terminating
resistor
in SDRAM
As shown in the above figure, when CL is 4, the effective ODT control signal
(MODT) to the SDRAM can be asserted at the same timing as the issue of the
WRITE command. If CL is 5 or greater, MODT is asserted after the issue of the
WRITE command. However, if CL is 3 or less, MODT needs to be asserted
before the issue of the WRITE command, which is not supported by this LSI.
Resistor ON
tAOND
= 2 cycles
3 cycles
for product
with CL = 4
High level
tAOFD
= 2.5 cycles
Figure 12.21 ODT Control Signal when CL = 4