Renesas SH7781 - Manual (Page 1131)

22. Serial I/O with FIFO (SIOF)
Rev.1.00 Jan. 10, 2008 Page 1101 of 1658
REJ09B0261-0100
22.2 Input/Output Pins
Table 22.1 shows the pin configuration.
Table 22.1 Pin Configuration
Pin Name* Function I/O Description
SIOF_MCLK Master clock Input Master clock input pin
SIOF_SCK Serial clock I/O Serial clock pin (common to
transmission/reception)
SIOF_SYNC Frame synchronous
signal
I/O Frame synchronous signal
(common to transmission/reception)
SIOF_TXD Transmit data Output Transmit data pin
SIOF_RXD Receive data Input Receive data pin
Note: * A pin group to be used can be selected according to the setting of PFC.
For details, see Peripheral Module Select Register 1 and Peripheral Module Select
Register 2, in section 28, General Purpose I/O Ports (GPIO).