Renesas SH7781 - Manual (Page 956)

19. Display Unit (DU)
Rev.1.00 Jan. 10, 2008 Page 926 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Internal
Update Description
22 to 20 DRGBA 0 R/W None Digital IRGV Output Timing Adjustment
000: Adjustment of output timing is not
performed.
The RGB signal is output at the rising edge
of the dot clock, with the reference timing.
001: The RGB signal is output at the rising edge,
delayed one dot clock cycle relative to the
reference timing.
010: The RGB signal is output at the rising edge,
delayed two dot clock cycles relative to the
reference timing.
011: The RGB signal is output at the rising edge,
delayed three dot clock cycles relative to
the reference timing.
100: The RGB signal is output at the falling
edge, preceding the reference timing by 1/2
dot clock cycle.
101: The RGB signal is output at the falling
edge, delayed 1/2 dot clock cycle relative to
the reference timing.
110: The RGB signal is output at the falling
edge, delayed (1+1/2) dot clock cycles
relative to the reference timing.
111: The RGB signal is output at the falling
edge, delayed (2+1/2) dot clock cycles
relative to the reference timing.
19
⎯ 0 R ⎯ Reserved
This bit is always read as 0. The write value
should always be 0.
18 to 16
⎯ All
0 R
⎯ Reserved
These bits are always read as undefined. The
write value should always be 0.
15 to 11
⎯ All
0 R
⎯ Reserved
These bits are always read as 0. The write value
should always be 0.