Renesas SH7781 - Manual (Page 564)

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 534 of 1658
REJ09B0261-0100
MCK0,
MCK1
MA[14:11]
MA[9:0]
MBA[2:0]
MCKE
MCS
MRAS
MCAS
MWE
MA[10]
ACT
bank A bank A
Invalid Invalid
MDQS[3:0]
MDQ[31:0]
MDM[3:0]
Invalid Invalid
SDRAM
command
Invalid
Invalid Invalid
Invalid Invalid Invalid
Invalid Invalid Invalid
Example of CL = 3
Valid Valid
Valid Valid
Valid Valid
Write data
bank A
WRITE WRITE
Valid
Valid
Valid
High level
Figure 12.11 Waveforms for 32-Byte Writing (When the Bus Width Is Set to 32 Bits)
Figure 12.12 shows waveforms during auto-refresh operation resulting from settings of the
SDRAM refresh control registers 0, 1, and 2. The DBSC2 issues a REF command automatically
after the PALL command is issued when at least one DDR2-SDRAM bank is activated before the
REF command. Consequently, there is no need to use software to manage precharging of all the
banks for the auto-refresh operation.