Renesas SH7781 - Manual (Page 1313)

25. Audio Codec Interface (HAC)
Rev.1.00 Jan. 10, 2008 Page 1283 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W* Description
31 to 23
⎯ All
0 R Reserved
These bits are always read as 0. The write value should
always be 0.
22 STARY 0 R/W Status Address Ready
0: HACCSAR (status address) is not ready.
1: HACCSAR (status address) is ready.
21 STDRY 0 R/W Status Data Ready
0: HACCSDR (status data) is not ready.
1: HACCSDR (status data) is ready.
20 PLRFRQ 0 R/W PCML RX Request
0: PCML RX data is not ready.
1: PCML RX data is ready and must be read. In DMA
mode, reading HACPCML automatically clears this
bit to 0.
19 PRRFRQ 0 R/W PCMR RX Request
0: PCMR RX data is not ready.
1: PCMR RX data is ready and must be read. In DMA
mode, reading HACPCMR automatically clears this
bit to 0.
18 to 14
⎯ All
0 R Reserved
These bits are always read as 0. The write value should
always be 0.
13 PLRFOV 0 R/W PCML RX Overrun
0: No PCML RX data overrun has occurred.
1: PCML RX data overrun has occurred because the
HAC has received new data from slot 3 before PCML
data is not read out.
12 PRRFOV 0 R/W PCMR RX Overrun
0: No PCMR RX data overrun has occurred.
1: PCMR RX data overrun has occurred because the
HAC has received new data from slot 4 before PCMR
data is not read out.
11 to 0
⎯ All
0 R Reserved
These bits are always read as 0. The write value should
always be 0.
Note: * This register is readable/writable. Writing 0 to the bit initializes it but writing 1 has no
effect.