Renesas SH7781 - Manual (Page 674)

13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 644 of 1658
REJ09B0261-0100
(6) Endian
This LSI supports both the big and little endian formats. Since the PCI local bus is inherently little
endian, the PCIC supports both byte swapping and non-byte swapping.
The endian format is specified by the TBS bit in PCICR.
31
MSB LSB
0
PCI bus data
SHwy data
1. Little endian
A' B' C' D' A B C
A' B' C' D' A B C D
A B C
PCI_Addr[2] = 1
PCI_Addr[2] = 0
31
MSB LSB
0
PCI bus data
SHwy data A B C D A' B' C' D'
A B C D A' B' C' D'
A B C
PCI_Addr[2] = 0
PCI_Addr[2] = 1
2. Big endian
Note: PCIAddr[2]: PCI bus AD[2]
D
D
Buffer data
Buffer data
D
Figure 13.13 Endian Conversion from PCI Bus to SuperHyway Bus
(Non-Byte Swapping: TBS = 0)