Renesas SH7781 - Manual (Page 1341)

26. Serial Sound Interface (SSI) Module
Rev.1.00 Jan. 10, 2008 Page 1311 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Description
24 DIRQ 0 R Data Interrupt Status Flag
This status flag indicates that the SSI module requires
that data be either read out or written in.
This bit is set to 1 regardless of the setting of DIEN bit,
so that polling will be possible.
The interrupt can be masked by clearing DIEN bit to 0,
but writing 0 in this bit will not clear the interrupt.
If DIRQ = 1 and DIEN = 1, then an interrupt will be
generated.
When TRMD = 0 (Receive Mode):
0: No unread data exists in SSIRDR.
1: Unread data exists in SSIRDR.
When TRMD = 1 (Transmit Mode):
0: The transmit buffer is full.
1: The transmit buffer is empty, and requires that data
be written in SSITDR.
23 to 4
⎯ 0
R Reserved
These bits are always read as an undefined value. The
write value should always be 0.
3
2
CHNO1
CHNO0
0
0
R
R
Channel Number
The number indicates the current channel.
When TRMD = 0 (Receive Mode):
This bit indicates to which channel the current data in
SSIRDR belongs. When the data in SSIRDR is updated
by transfer from the shift register, this value will change.
When TRMD = 1 (Transmit Mode):
This bit indicates the data of which channel should be
written in SSITDR. When data is copied to the shift
register, regardless whether the data is written in
SSITDR, this value will change.